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Parent page: Finalizing the Board Design. Via stitching is a technique used to tie together larger copper areas on different layers, in effect creating a strong vertical connection through the board structure, helping maintain a low impedance and short return loops. Via stitching can also be used to tie areas of copper that might otherwise be isolated from their net to that net. Via shielding has a different function, in RF designs it is used to help reduce crosstalk and electromagnetic interference in a route that is carrying an RF signal.

A via shield, also known as a via fence or a picket fence, is created by placing one or more rows of vias alongside the signal's route path. In Altium Designer, this is referred to as via shielding. Altium Designer supports both via stitching and via shielding. In the image below, shielding vias are highlighted, move the cursor over the image to highlight the stitching vias that have been added to this board.

Use the Via Stitching and Via Shielding commands to stitch copper on different layers, and to add a wall of shielding vias adjacent to a route path hover to highlight shielding vias. Via stitching is run as a post-process, filling free areas of copper with stitching vias.

For via stitching to be possible, there must be overlapping regions of copper that are attached to the specified net, on different layers. Supported regions of copper include Fills, Polygons and Power Planes. Using the selected net, the stitching algorithm identifies all Fills, Polygons and Power Planes attached to that net and attempts to connect them through the board, using the specified via and stitching pattern.

Notes about the Add Stitching to Net dialog settings:. Each set of stitching vias are added to a union, set the PCB panel to Unions mode to locate and examine the vias included in a via stitching set. A stitching set can be removed by running the Tools » Via Stitching » Remove Via Stitching Group command, then clicking on any via in that set.

As well as covering the entire board, stitching vias can be constrained to a user-defined area. When the stitching is within a user-defined area, that area of vias can be interactively moved and resized, if required. Enable the Constrain Area option to restrict stitching vias to a user-defined area.

To constrain via stitching to a specific area, enable the Constrain Area checkbox in the Add Stitching to Net dialog, as shown above. As soon as you enable this option the dialog will close and the cursor will change to a crosshair, ready to define the area - note the Status bar, it will prompt Select the first point of the area. The process of defining a via stitching area is the same as defining a solid region or a polygon, you:.

Once the area is defined you will return to the Add Stitching to Net dialog, so you can configure the rest of the settings. Click OK when this is complete, Altium Designer will then analyze the area, identify potential via sites, and place the stitching vias. The set of vias in each unique area of via stitching are clustered into a Union a set of objects that the PCB editor recognizes as a single group. The entire union can be moved, and the area can also be resized.

Drag a selection window to select a stitching area, then move or resize by positioning the mouse to get the correct cursor. The vias will be placed along both sides of the chosen net, wherever it is possible to place a via that complies with the applicable design rules. Notes about the Add Shielding to Net dialog, and using shielding vias:. This is actually a very good rule for stitching any ground fill to the ground plane on a multi-layer design.

NB: C speed of light will be approx. As well as adding shielding vias along each side of the routing, you can also include shielding copper, as shown in the image below. To do this, enable the Add shielding copper option. This copper is created as a polygon, so it obeys the applicable Clearance and Polygon Connect Style design rules. The Add shielding copper option will add a polygon that encloses the shielding vias. The polygon edge that is away from the shielded net will touch the edge of the vias.

The polygon edge that is adjacent to the shielded net will be set back from the net by the applicable Clearance design rule. If the Add clearance cutout option is also enabled, the polygon will instead be set back from the shielded net by the Distance setting in the Add Shielding to Net dialog.

Hover the cursor over the image below to see the difference. Shielding vias around a net with the clearance cutout option enabled, move the cursor over the image to disable the clearance cutout option. The style of the connection from the shielding vias to the shielding copper polygon can be controlled by including a Polygon Connect Style design rule, targeted at the shielding vias and polygon.

Use the InViaShielding query keyword to scope this design rule, so that it specifically targets those vias and that polgyon. Each via in a stitching or shielding array is identified by the addition of a string to the net name, such as [VS1], as shown in the image below, where:. All vias that are part of that array will select if the Select checkbox is enabled in the panel as shown in the image below. Alternatively, double click on any via in the array to open the Properties panel and edit the array.

Use the PCB panel in Unions mode to select all vias in a stitching or shielding array. In this image, all four via shielding unions are selected. The properties of a stitching or shielding via set can be edited once it has been selected, in the Via Stitching or the Via Shielding mode of the Properties panel. An example of an edit being performed to a via shielding. As soon as any property has been edited in the panel, the Changes pending message and buttons appear at the bottom of the panel - use the appropriate button to complete your editing action.

The following collapsible sections contain information about the Via Shielding options and controls available:. The following collapsible sections contain information about the Via Stitching options and controls available:. Once stitching is complete, you will need to re-pour the polygons if the applicable Polygon Connect Style design rule specifies a relief connection style. This can be done using the commands in the Tools » Polygon Pours sub-menu. Using Altium Documentation. Shielding Parameters.

Net — the net to have shielding vias placed around. Stagger alternate rows — alternate rows of shielding vias are offset by half of the Grid value when this option is enabled. Row Spacing — spacing between rows of shielding vias edge to edge separation when the Rows setting is greater than 1.

Distance — separation from the edge of the shielded net track segments, to the edge of the shielding vias. Grid — the distance between the edges of adjacent shielding vias. Shielding vias will not be placed in violation of applicable design rules; if a potential via site would result in a violation then that site is skipped. Rows — number of rows of shielding vias.

Add Shielding — place a polygon over the area occupied by the shielding vias, connected to the net specified in the Via Net field.

The polygon is defined in accordance with the applicable Clearance constraint and Polygon Connect Style design rules. Add Clearance Cutout — include a polygon cutout around the shielded net, set back from the net by the distance specified in the Distance field. Use this when you require a different clearance from the applicable Clearance constraint design rule.

Net — the net being shielded by the shielding vias. Net Class — if the chosen Net is a member of a Net Class, it will be displayed in this field. Via Template. Template — displays the currently chosen via template. Use the drop-down to change the assigned via template. Library — displays to which library the via template is linked and includes the option to Unlink the template from said library. Net — the net that the shielding vias are connected to.

Via Type — use the drop-down to select the type of via from those available in the layer stack. Via Types — click to open the Layer Stack to configure the required via types for the active layer stack. Hole Information. Hole Size — size of the hole in the shielding vias.

Tolerance — negative and positive hole size tolerances allowed for the shielding vias. Size and Shape. Size and Shape — vias are one of three styles: Simple — the via diameter is the same on all layers Top-Middle-Bottom — the via diameter can be specified for the Top layer, Middle all internal layers , and Bottom layer.

Full Stack — the via diameter can be specified for every signal layer. Diameter — diameter of the shielding vias. Thermal Relief — check the Direct box then click to open the Connect Style dialog to specify the connection style. Solder Mask Expansion. Rule — enable this option to allow the existing solder mask expansion rule to take effect on the shielding vias. Manual — enable this option to edit the mask expansion values below for these shielding vias.

Top — enter the required mask expansion for the Top Layer. Bottom — enter the required mask expansion for the Bottom Layer. Top Tented — if this checkbox is enabled, the mask is closed on the Top Layer for these shielding vias. Bottom Tented — if this checkbox is enabled, the mask is closed on the Bottom Layer for these shielding vias. Linked — if the Linked option is enabled, the same expansion value is used for both the Top and Bottom layers.

From Hole Edge — enable this option to calculate the mask expansion from the edge of the drill hole instead of the edge of the via donut. Stitching Parameters. Constrain Area — enable to constrain via stitching to a specific area. After selecting the option, you will be taken to the design space. After using the cross-hair cursor to define the constrain area, right-click to return to the dialog. Edit Area — click to edit the constrain area. The stitching pattern will placed within the constrain area, starting at an offset of the specified X and Y amount.